This invention relates to the field of integrated circuit design. More particularly the invention relates to optimizing circuit design based on circuit timing.
When integrated circuits such application specific integrated circuits are designed, they typically undergo an optimization process. During the optimization process, different characteristics of the integrated circuit are tested to determine whether they meet the design criteria for the integrated circuit. If all of the tested characteristics of the integrated circuit meet all of the design criteria, then perhaps the design of the integrated circuit is not altered. More commonly, however, the characteristics of the integrated circuit are tested and then the design of the integrated circuit is modified in some specific manner, in an iterative procedure called optimization that is intended to optimize at least a given set of the tested characteristics, as referenced against the design criteria. This iterative procedure is often referred to as a resynthesis of the integrated circuit.
One of the characteristics of the integrated circuit that is typically tested is the timing of the integrated circuit. The timing of the integrated circuit relates generally to the temporal relationships between the various electrical signals that are applied at different times to different subsets of elements within the integrated circuit. For example, a given design for an integrated circuit typically specifies that certain electrical signals arrive at certain elements within the integrated circuit within specified time boundaries, in order for the integrated circuit to produce the proper response according to the design criteria. Thus, testing of the integrated circuit for the proper temporal relationships of the applied and produced electrical signals, and then modifying the integrated circuit in an attempt to optimize those temporal relationships is called timing driven resynthesis herein.
Because of the complexity of state of the art integrated circuits, the timing driven resynthesis process may comprise an extreme number of the iterative procedures described above. What is needed, therefore, is a method whereby the temporal characteristics of the various electrical signals can be determined in a relatively short length of time, so that the iterative process of timing driven resynthesis can proceed without undue delay.
The above and other needs are met by a method of computing timing delays of timing edges of a path of an integrated circuit design. According to the method, all pins within the path are identified, and all timing edges defined by the pins within the path are identified. All pins within the path that are a leading pin of one of the time edges in the path are also identified. For each given pin within the path, a tabulation is made of a number of pins that are upstream from the given pin along a contiguous series of the timing edges in the path. A computational rank is assigned to the given pin based upon the tabulated number for the given pin. The timing edges are ordered for computation based upon the computational rank of the leading pin of each timing edge in the path, to produce an ordered list of timing edges. The timing delays of the timing edges of the path are computed according to the ordered list of timing edges.
In this manner, the timing edges are ordered for either initial computation or recomputation so that dependent timing computations are not accomplished prior to the more independent computations on which they ultimately depend. This method produces a fast timing recomputation procedure whereby the often repeated timing recomputation procedure does not take an unduly long period of time to accomplish.
According to another aspect of the invention, there is presented a method of resynthesizing an integrated circuit design. A timing output cone is identified based on a starting set of pins of the integrated circuit design, and a timing input cone is identified based on an ending set of pins of the integrated circuit design. The timing input cone and the timing output cone are intersected to produce an intersection defining a path. The timing delays of timing edges of the path are computed using the method as described above. The arrival times of the pins of the path are computed based on the timing delays of the timing edges of the path, and the departure times of the pins of the path are also computed based on the timing delays of the timing edges of the path. The total delay of the path is computed from the arrival times and the departure time of the pins of the path. The total delay of the path is compared to a required time of the path. If the total delay of the path is greater than the required time of the path, then a change is made to the integrated circuit design, and the total delay of the path is recomputed in an iterative fashion until the total delay of the path is no greater than the required time of the path.
According to another aspect of the invention, a computer program and a computing device for computing timing delays of timing edges of a path of an integrated circuit design are also described.